Recently, a method of implanting ions through a field oxidation film to underneath is widely used for forming a channel stopper layer under the field oxidation film (this ion implantation for forming the channel stopper layer is hereinafter referred to as channel stopper implantation) relating to element isolation in a manufacturing process of a metal oxide semiconductor field effect transistor (MOS FET). The reason is that this method has effects of suppressing a narrow channel effect and improving junction breakdown strength, as compared with a method of carrying out the channel stopper implantation before forming the field oxide film.
As to the channel stopper implantation after forming the field oxide film, various methods have been proposed. For example, the Japanese Publication for Laid-Open Patent Application No. 3-257846/1991 (Tokukaihei No. 3-257846) and the Japanese Publication for Laid-Open Patent Application No. 4-22170/1992 (Tokukaihei No. 4-22170) disclose a method of using a resist mask so that impurities would not enter an active region. The Japanese Publications for Laid-Open Patent Applications No. 5-283519/1993 (Tokukaihei No. 5-283519), No. 5-218194/1993 (Tokukaihei No. 5-218194), and No. 6-5588/1994 (Tokukaihei No. 6-5588) disclose a method of carrying out the ion implantation with an oxidation resistance mask remaining, which has been used during the formation of the field oxide film, so as to prevent impurities from entering an active region.
Besides, there has been proposed another method which is disclosed by the Japanese Publication for Laid-Open Patent Application No. 3-142856/1991 (Tokukaihei No. 3-142856). According to the method, a field oxide film is formed thicker than an intended thickness, and channel stopper implantation is carried out with a high energy. Thereafter, the field oxide film is etched to the intended film thickness. In this case, even though impurities enter an active region, a position at which they are implanted is considerably deep in the active region. Therefore, it is possible to suppress an increase in a junction capacitance (junction capacitance in a direction of an interface between a lower part of a diffusion layer and a substrate).
The method used here, in which the resist mask is used, requires precision in mask alignment. Therefore, it is not suitable for micromachinning. As to the method of ion implantation with an oxidation resistant mask remaining is not practical, since a thick oxidation resistant mask, that is required in the case where an implantation energy is high, causes stress on the substrate during thermal oxidation. On the other hand, a thinner field oxide film, that is required in the case where the implantation energy is relatively low, makes it difficult to set a level of the implantation energy and a film thickness of the oxide film so that they match each other.
Therefore, a method on the premise that the impurities enter the active region is practical. The following description will explain a conventional technique on the premise that the impurities enter the active region, which is disclosed by the Japanese Publication for laid-Open Patent Application No. 3-142856/1991 (Tokukaihei No. 3-142856).
To start with, a pad oxide film 22 and a silicon nitride film 23 are deposited on a P-type silicon substrate (or P-type well) 21, and the silicon nitride film 23 is opened so as to form an element isolating region, in which a field oxide film 24 is formed (see FIG. 7(a)). Herein, the field oxide film 24 is formed thicker than an intended thickness of the film. For example, in the case where the intended thickness is 3000 .ANG., the field oxide film 24 is formed 4000 .ANG. thick.
Next, the pad oxide film 22 and the silicon nitride film 23 are removed. Ions of boron are implanted by the dose quantity of about 4.times.10.sup.12 cm.sup.-2 through the field oxide film 24. Herein, the implantation is performed at an energy of about 150 keV when the thickness of the field oxide film 24 is about 4000 .ANG. (see FIG. 7(b)). Note that 25a represents the implanted boron ions.
Then, the field oxide film 24 is etched back to the intended film thickness by wet etching with hydrofluoric acid or by RIE (reactive ion etching). Note that "a" in FIG. 7(c) represents a thickness of an etched-back portion of the field oxide film 24, which is about 1000 .ANG., and "b" represents a thickness of the field oxide film 24 after the etching back, which is about 3000 .ANG..
Subsequently, a gate oxide film 26 and a gate electrode 27 are formed, and thereafter, N.sup.+ diffusion layers 28 to serve as source/drain regions are formed (see FIG. 7(d)). Note that as shown in FIG. 7(d), the boron ions 25a implanted through the channel stopper implantation are diffused by thermal annealings in the process of forming the MOS FET (for example, a thermal annealing for activating the N.sup.+ diffusion layer 28), thereby forming an impurity layer (a boron implantation layer serving as a channel stopper layer) 25b which spreads to some extent.
In addition, as illustrated in FIG. 7(d), the boron implantation layer 25b serving as the channel stopper layer is formed in a considerably deep part in the active region (where the MOS FET is formed). Therefore, problems such as an increase in the junction capacitance (junction capacitance in a direction of an interface between a lower part of a diffusion layer and a substrate) can be solved.
However, according to the aforementioned conventional manufacturing method, the channel stopper implantation at a high energy is applied with the field oxide film 24 formed thicker, and thereafter the field oxide film 24 is etched back to the intended thickness. This causes the field oxide film 24 to be etched back not only in a perpendicular direction but also in lateral directions, resulting in dimensional changes thereof. In FIG. 7(c), "c" represents a degree of the etching in lateral directions.
Therefore, in the case where the dimensional change varies, it causes a gate width of the MOS FET to vary, thereby causing characteristics of the MOS FET to vary. Moreover, since a width of the element isolating region varies with the dimensional changes, it is necessary to form the field oxide film 24 larger in size than the intended size, fearing that the field oxide film 24 might be excessively etched back. In any case, as long as the dimensional changes occur as a result of the etching back, the aforementioned method is not suitable for micromachinning.
On the other hand, in nonvolatile memories such as EEPROM (electrically erasable programmable read only memory), a high voltage is applied also to the diffusion layer upon writing or erasing data. Therefore, source/drain breakdown strength (junction breakdown strength and punch-through breakdown strength) and element isolation breakdown strength (field inversion voltage) should be increased. At present, breakdown strength of not less than 15 V is required. In order to increase the element isolation breakdown strength, it is necessary to thicken the field oxide film or to increase the implantation dose of the impurity for formation of the channel stopper layer, but as the field oxide film becomes thicker, a bird's peak tends to get longer, thereby increasing the dimensional changes.
Moreover, in the case where the channel stopper layer is formed deep in a channel region so that the transistor is less affected, it is required, in forming a microscopic transistor, to further carry out additional channel implantation and the like.